1. Field of the Invention
This invention relates generally to asynchronous transmission of data between two computers having asynchronous clocks. More particularly the present invention relates to an interface logic system which, with a minimum of components and inter-connecting lines, verifies that valid information transfer control signals exist and assures proper completion of a data strobe pulse.
2. Description of the Prior Art
Computers and/or computer related equipment must be synchronized with one another in order to successfully transmit and receive control signals and data. If both computers have a master clock as a common time base, the problem is not critical. If the two computers are asynchronous, i.e., each having their own internal time base, and the data transfer rate is intermittent or asynchronous, synchronization becomes a problem.
An aspect of the asynchronous problem which creates further complications is that false or transient pulses often appear on the lines interconnecting the two computers. Such transients, if mistakenly identified as a control signal, may result in a data transfer sequence to an upsuspecting computer at a totally inopportune time. This aspect of the problem, prior to this invention, has plagued most prior art approaches.
A common prior art approach for transferring signals between two asynchronous computers is to use a special encoding format for the signals to be transmitted. The special format includes synchronizing information which is conbined with any control signals that are to be sent between the computers. Within a receiving computer the synchronizing information is separated from the control signals, and it is employed to correct a locally generated clock so that the local clock is synchronized to the remote computer's clock. In such devices it is common to employ the corrected clock as a shift command for signal buffer shift registers. Incoming signals are clocked into the buffer shift registers, and any time differences between the clocks of both computers are absorbed by the signal buffer registers.
Such prior art solutions are unattractive because signal buffer registers waste significant computer time and represent additional complex equipment. Furthermore, the encoding, decoding and other handling of the additional synchronizing information is undesirable. Shifting the local clock also involves costly and signal-sensitive synchronizing loops and this is undesirable. In summary, such prior art schemes typically exemplify complex interface systems as compared with the features of this invention.